Rambus launches Terabyte Bandwidth Initiative

Published 28 November 2007

Technology initiative will facilitate blazing-fast data rates of 16 Gbps and enable a future memory architecture which can deliver terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC)

Los Altos, California-based Rambus (NASDAQ: RMBS) today unveiled its Terabyte Bandwidth Initiative. This technology initiative includes the development of new memory signaling innovations which will facilitate blazing-fast data rates of 16 Gbps and enable a future memory architecture which can deliver an unprecedented terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC). Rambus already holds the record for the world’s fastest memory — the Rambus 4.8 GHz XDR DRAM — but with the technology developed through this initiative, Rambus will increase the data rate of memory above that record. Rambus will demonstrate a silicon test vehicle for its Terabyte Bandwidth Initiative today at RDF-Japan. The Terabyte Bandwidth Initiative includes innovations for a new generation of memory systems, such as:

* 32X data rate — 32 data bits per input clock cycle
* Fully Differential Memory Architecture (FDMA) — the industry’s first differential signaling for both data and command/address (C/A)
* FlexLink C/A — The industry’s first full-speed, point-to-point C/A link

For more information on the Terabyte Bandwidth Initiative and its innovations see the company’s Web site.