Configurable cores boost processor power, aid biometrics

Published 7 March 2006

Clock rate determines performance in compute-intensive applications. Right? Wrong: Software configurable processors are challenging this particular conventional wisdom. A simulation of the Stretch S5610 processor from Mountain View, California-based Stretch achieved an EEMBC benchmark score of (the equivalent of) 877 Telemarks back in April 2004, putting it right at the top of the table. Bearing in mind the clock speed was only 300 MHz, and that close rivals had clock speeds of 2 GHz, the software-programmable processor seems even more impressive. Now that the hardware is available, can it live up to the performance that was promised?

Sunnyvale, California-based biometrics company A4Vision has recently put the Stretch architecture to the test in image processing in its facial scanning system. A4’s system shoots an invisible structured light pattern onto the face which is distorted by the face’s surface geometry. A video camera precisely records the pattern distortion which is put into a 3D reconstruction algorithm. In security systems, results are compared with a template stored on the person’s smart card to verify identity. This kind of image processing is demanding on the processors used, especially as the data is captured in 3D while a person is moving. This means real time calculations are particularly important.

The original implementation was a 3 GHz Pentium, allowing the PC to calculate sixty surfaces per second while the Stretch implementation calculates ten. Stretch software-programmable processors are designed to accelerate the number-crunching in compute-intensive applications. The processor silicon contains an amount of programmable logic called the ISEF (instruction set extension fabric). The designer picks out the ‘hot spots’ in their application code and the Stretch compiler converts that intensive function into a logic-based instruction which is programmed into the ISEF, as an extension to the instruction set of the processor. “For each function that is identified as a hot spot, the calling parameters end up being translated into register references, and the body of it is turned into hardware,” explains Gary Banta, CEO of Stretch. “The compiler creates a configuration bitstream for the ISEF. What was originally in your code as a function call is now being treated as a new instruction.”

The aim is the performance of logic combined with C/C++ development simplicity. The embedded software engineer can define an optimized processor for their application, using only their code and the Stretch compiler and chip. Just compare this quick and simple development cycle to that of an FPGA or an ASIC, and it is clear to see the benefits that this development cycle brings.

The power and simplicity of C/C++-programmable processors were obvious in A4Vision case. The calculations that were involved in A4Vision were not classic MAC (multiply-accumulate)-centric functions. “If they tried to do it on any other DSP or programmable product out there, they couldn’t fill up a board with enough of them to be able to do it,” says Fred Palma, vice president of Engineering at A4Vision.

—read more in this Components in Electronics report; read more about reconfigurable cores in this EETimes report; and see the Web site of Stretch |A4Vision | EEMBC